Exemplary embodiments relate to the column address circuit of a semiconductor memory device and a method of generating column addresses and, more particularly, to the column address circuit of a semiconductor memory device and a method of generating column addresses which are capable of securing adequate margin for the column address when data is outputted.
Among various types of semiconductor memory devices, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific intervals.
A column address circuit of a nonvolatile memory device may receive a start column address from outside and increase a column address whenever an internal clock CK4CNT generated in response to a read enable signal RE or a write enable signal WE is toggled.
In the read operation of the nonvolatile memory device, a determination as to whether a column address, counted and generated by an internal circuit, is a normal address or a repair address is to be performed. Thus, the column address is to be sent to a plane through a repair address comparator. For this reason, column addresses may take longer in reaching a plane due to use of the repair address comparator, and an adequate margin for performing the count operation of the column address circuit at a high-speed operation may be compromised. Consequently, an error may occur in the data output operation.